module StereoVisionTop	(				
					
					input wire	iCLK_50,
//					input wire	iCLK_28,
//					input wire	iCLK_50_2,
		////////////////////	7-SEG Dispaly	////////////////////
					output	wire	[6:0]	oHEX0_D,		//	Seven Segment Digit 0
//					output	wire			oHEX0_DP,		//  Seven Segment Digit 0 decimal point
					output	wire	[6:0]	oHEX1_D,		//	Seven Segment Digit 1
//					output	wire			oHEX1_DP,		//  Seven Segment Digit 1 decimal point
					output	wire	[6:0]	oHEX2_D,		//	Seven Segment Digit 2
//					output	wire			oHEX2_DP,		//  Seven Segment Digit 2 decimal point
					output	wire	[6:0]	oHEX3_D,		//	Seven Segment Digit 3
//					output	wire			oHEX3_DP,		//  Seven Segment Digit 3 decimal point
					output	wire	[6:0]	oHEX4_D,		//	Seven Segment Digit 4
//					output	wire			oHEX4_DP,		//  Seven Segment Digit 4 decimal point
					output	wire	[6:0]	oHEX5_D,		//	Seven Segment Digit 5
//					output	wire			oHEX5_DP,		//  Seven Segment Digit 5 decimal point
					output	wire	[6:0]	oHEX6_D,		//	Seven Segment Digit 6
//					output	wire			oHEX6_DP,		//  Seven Segment Digit 6 decimal point
					output	wire	[6:0]	oHEX7_D,		//	Seven Segment Digit 7
//					output	wire			oHEX7_DP,		//  Seven Segment Digit 7 decimal point

// VGA
					output		[9:0]	oVGA_R,
					output		[9:0]	oVGA_G,
					output		[9:0]	oVGA_B,
					output	wire		oVGA_HS,
					output	wire		oVGA_VS,
					output				oVGA_SYNC_N,
					output				oVGA_BLANK_N,
					output				oVGA_CLOCK,
// --SRAM interface ------						
					output wire [18:0]	oSRAM_A,		// output address
					inout  wire	[31:0]	SRAM_DQ,		// DATA INPUT and OUTPUT port
					output wire 		oSRAM_ADSC_N,	// controller address status
					output wire			oSRAM_ADSP_N,	// processor address status
					output wire			oSRAM_ADV_N,	// advance input signal (burst address advance)
					output wire [3:0]	oSRAM_BE_N, 	// Byte write enable
					output wire			oSRAM_CE1_N, 	// chip enable 1
					output wire			oSRAM_CE2,		// chip enable 2
					output wire 		oSRAM_CE3_N,	// chip enable 3
					output wire			oSRAM_CLK,		// clock to SRAM
					inout  wire	[3:0]	SRAM_DPA,		// Parity data
					output wire	 		oSRAM_GW_N,		// global write
					output wire			oSRAM_OE_N,		// output enable
					output wire			oSRAM_WE_N,	// write enable
// user interface
					input  wire [17:0]	iSW,
					input  wire [3:0]	iKEY,
//					output wire	[8:0]	LEDG,
					output wire	[17:0]	LEDR,
////////////////////////	GPIO	////////////////////////////////
					inout		[31:0]	GPIO_0,					//	GPIO Connection 0 I/O
					input				GPIO_CLKIN_N0,     		//	GPIO Connection 0 Clock Input 0
					input				GPIO_CLKIN_P0,          //	GPIO Connection 0 Clock Input 1
					inout				GPIO_CLKOUT_N0,     	//	GPIO Connection 0 Clock Output 0
					inout				GPIO_CLKOUT_P0,         //	GPIO Connection 0 Clock Output 1
					inout		[31:0]	GPIO_1,					//	GPIO Connection 1 I/O
					input				GPIO_CLKIN_N1,          //	GPIO Connection 1 Clock Input 0
					input				GPIO_CLKIN_P1,          //	GPIO Connection 1 Clock Input 1
					inout				GPIO_CLKOUT_N1,         //	GPIO Connection 1 Clock Output 0
					inout				GPIO_CLKOUT_P1         //	GPIO Connection 1 Clock Output 1
				);
				
//-------------------------------------------------------------
//Internal connection
wire	CLK_25,SRAM_CLK;
wire	DISP_CLK,REF_CLK;
wire	RST_N,DLY_RST_0,DLY_RST_1,DLY_RST_2,DLY_RST_3,DLY_RST_4;
assign	oVGA_CLOCK	= ~CLK_25;				
//============================================================
//						CAMERA0
//============================================================

//-------------------CAMERA0 INTERFACE SIGNALS---------------------------
wire	[11:0]	D5M_DATA0;
wire			D5M_SDATA0;
wire			D5M_SCLK0;
wire			D5M_FVAL0;
wire			D5M_LVAL0;
wire 			D5M_PIXCLK0;



assign	D5M_DATA0[0]	=	GPIO_0[11];
assign	D5M_DATA0[1]	=	GPIO_0[10];
assign	D5M_DATA0[2]	=	GPIO_0[9];
assign	D5M_DATA0[3]	=	GPIO_0[8];
assign	D5M_DATA0[4]	=	GPIO_0[7];
assign	D5M_DATA0[5]	=	GPIO_0[6];
assign	D5M_DATA0[6]	=	GPIO_0[5];
assign	D5M_DATA0[7]	=	GPIO_0[4];
assign	D5M_DATA0[8]	=	GPIO_0[3];
assign	D5M_DATA0[9]	=	GPIO_0[2];
assign	D5M_DATA0[10]	=	GPIO_0[1];
assign	D5M_DATA0[11]	=	GPIO_0[0];

assign	GPIO_CLKOUT_N0	=	CLK_25;
assign	D5M_FVAL0		=	GPIO_0[18];
assign	D5M_LVAL0		=	GPIO_0[17];
assign	D5M_PIXCLK0		=	GPIO_CLKIN_N0;




assign	GPIO_0[15]		=	1'b1;  // tRIGGER
assign	GPIO_0[14]		=	DLY_RST_1;//RESET_n

//------------------------------------------------------------------------

//---------------------------CAMERA0 Data Buffer--------------------------
always@(posedge D5M_PIXCLK0)
begin
	rD5M_DATA0	<=	D5M_DATA0;
	rD5M_FVAL0	<=	D5M_FVAL0;
	rD5M_LVAL0	<=	D5M_LVAL0;
end
//-------------------------------------------------------------------------

//---------------------CAMERA0 CAPTURE MODULE and SIGNALS-----------------
reg [11:0] 		rD5M_DATA0; 	// intermediate signal
reg 			rD5M_LVAL0; 	// intermediate signal
reg 			rD5M_FVAL0; 	// intermediate signal
wire [9:0] 		cD5M_DATA0; 	// intermediate signal
wire 			cD5M_DVAL0; 	// intermediate signal
wire [15:0] 	X_Cont0; 		// x position of current pixel from camera
wire [15:0] 	Y_Cont0; 		// y position of current pixel from camera
wire [31:0] 	Frame_Cont0; 	// frame count
		
CCD_Capture			U0A	(	.oDATA(cD5M_DATA0),
							.oDVAL(cD5M_DVAL0),
							.oX_Cont(X_Cont0),
							.oY_Cont(Y_Cont0),
							.oFrame_Cont(Frame_Cont0),
							.iDATA(rD5M_DATA0),
							.iFVAL(rD5M_FVAL0),
							.iLVAL(rD5M_LVAL0),
							.iSTART(!iKEY[3]),
							.iEND(!iKEY[2]),
							.iCLK(D5M_PIXCLK0),//.iCLK(~CCD_PIXCLK),//CCD_PIXCLK_COMB),
							.iRST(DLY_RST_2)
						);
//----------------------------------------------------------------------------
//---------------------CAMERA0 RAW2RGB MODULE and SIGNALS---------------------				
wire [7:0] 	mD5M_R0; 		// intermediate signal
wire [7:0] 	mD5M_G0; 		// intermediate signal
wire [7:0] 	mD5M_B0; 		// intermediate signal	
wire 		mD5M_DVAL0; 	// intermediate signal	
							
RAW2RGB				U1A	(	.iCLK(D5M_PIXCLK0),
							.iRST(DLY_RST_1),
							.iDATA(cD5M_DATA0),
							.iDVAL(cD5M_DVAL0),
							.oRed(mD5M_R0),
							.oGreen(mD5M_G0),
							.oBlue(mD5M_B0),
							.oDVAL(mD5M_DVAL0),
							.oLine_No(Line_No0),
							.iX_Cont(X_Cont0),
							.iY_Cont(Y_Cont0)
													
);						
//----------------------------------------------------------------------------

//----------------------------------------------------------------------------
wire 			ff_full0;
wire 	[10:0]	Line_No0;
reg		[7:0]	GRAY0;

always @(posedge D5M_PIXCLK0 or negedge RST_N) begin
	if (!RST_N)
		GRAY0	<= 0;
	else 
		GRAY0	<= ((mD5M_R0>>2)+(mD5M_R0>>4))+((mD5M_G0>>1)+(mD5M_G0>>4))+(mD5M_B0>>3);
end

reg 		gD5M_DVAL0; 	// intermediate signal	

always @(posedge D5M_PIXCLK0 ) begin
		gD5M_DVAL0	<= mD5M_DVAL0;
end	

reg	 [1:0]	byte_no0,pre_byte_no0;
always @(posedge D5M_PIXCLK0 or negedge RST_N)begin
	if (!RST_N)begin
		byte_no0 	<= 0;
	end
	else  begin
		if (gD5M_DVAL0)begin
		byte_no0	<=	byte_no0 + 2'b01;
			case (byte_no0)
				2'b00: w_data0[7:0]		<=	GRAY0[7:0];
				2'b01: w_data0[15:8]	<=	GRAY0[7:0];
				2'b10: w_data0[23:16]	<=	GRAY0[7:0];
				2'b11: w_data0[31:24]	<=	GRAY0[7:0];
			endcase
		end
	end
end
assign 		w_BE_N5 = 4'b0000;
reg  [31:0]	w_data0;
reg			winc0;

always @ (posedge D5M_PIXCLK0) begin
	pre_byte_no0 <= byte_no0;
	if ((byte_no0 == 2'b00)&&(pre_byte_no0 == 2'b11))
		winc0 <= 1;
	else
		winc0 <= 0;
end		


always @ (posedge SRAM_CLK or negedge Line_No0[0]) begin
  if (!Line_No0[0]) begin
    w_address5 	<= {Line_No0[10:1],7'b0000000}+{Line_No0[10:1],5'b00000}+19'h12C00;	// 640 pixels
  end
  else begin
	if (w_port_avai5 && !w_stop5)
		w_address5 <= w_address5 + 1'b1;
  end
end


//------------------------------------------------------------------------------------------------------------------------

//---------------------------CAMERA_FIFO0------------------------------------------	

fifo1	U3A (
					.rdata(w_data5),
					.wfull(ff_full0),
					.rempty(w_stop5),
					.wdata(w_data0),
					.winc(winc0), .wclk(~D5M_PIXCLK0), .wrst_n(DLY_RST_1),
					.rinc(w_port_avai5), .rclk(SRAM_CLK), .rrst_n(DLY_RST_1)
				 );	
//----------------------------------------------------------------------------
//============================================================
//						CAMERA1
//============================================================							

//-------------------CAMERA1 INTERFACE SIGNALS---------------------------
wire	[11:0]	D5M_DATA1;
wire			D5M_SDATA1;
wire			D5M_SCLK1;
wire			D5M_FVAL1;
wire			D5M_LVAL1;
wire 			D5M_PIXCLK1;

//
assign	D5M_DATA1[0]	=	GPIO_1[11];
assign	D5M_DATA1[1]	=	GPIO_1[10];
assign	D5M_DATA1[2]	=	GPIO_1[9];
assign	D5M_DATA1[3]	=	GPIO_1[8];
assign	D5M_DATA1[4]	=	GPIO_1[7];
assign	D5M_DATA1[5]	=	GPIO_1[6];
assign	D5M_DATA1[6]	=	GPIO_1[5];
assign	D5M_DATA1[7]	=	GPIO_1[4];
assign	D5M_DATA1[8]	=	GPIO_1[3];
assign	D5M_DATA1[9]	=	GPIO_1[2];
assign	D5M_DATA1[10]	=	GPIO_1[1];
assign	D5M_DATA1[11]	=	GPIO_1[0];
//
assign	GPIO_CLKOUT_N1	=	CLK_25;
assign	D5M_FVAL1		=	GPIO_1[18];
assign	D5M_LVAL1		=	GPIO_1[17];
assign	D5M_PIXCLK1		=	GPIO_CLKIN_N1;


	
assign	GPIO_1[15]		=	1'b1;  		// tRIGGER
assign	GPIO_1[14]		=	DLY_RST_1;	//RESET_n

//------------------------------------------------------------------------

//---------------------------CAMERA1 Data Buffer--------------------------
always@(posedge D5M_PIXCLK1)
begin
	rD5M_DATA1	<=	D5M_DATA1;
	rD5M_FVAL1	<=	D5M_FVAL1;
	rD5M_LVAL1	<=	D5M_LVAL1;
end
////-------------------------------------------------------------------------
//
////---------------------CAMERA1 CAPTURE MODULE and SIGNALS-----------------
reg [11:0] 		rD5M_DATA1; 	// intermediate signal
reg 			rD5M_LVAL1; 	// intermediate signal
reg 			rD5M_FVAL1; 	// intermediate signal
wire [9:0] 		cD5M_DATA1; 	// intermediate signal
wire 			cD5M_DVAL1; 	// intermediate signal
wire [15:0] 	X_Cont1; 		// x position of current pixel from camera
wire [15:0] 	Y_Cont1; 		// y position of current pixel from camera
wire [31:0] 	Frame_Cont1; 	// frame count											
CCD_Capture			U0B	(	.oDATA(cD5M_DATA1),
							.oDVAL(cD5M_DVAL1),
							.oX_Cont(X_Cont1),
							.oY_Cont(Y_Cont1),
							.oFrame_Cont(Frame_Cont1),
							.iDATA(rD5M_DATA1),
							.iFVAL(rD5M_FVAL1),
							.iLVAL(rD5M_LVAL1),
							.iSTART(!iKEY[3]),
							.iEND(!iKEY[2]),
							.iCLK(~D5M_PIXCLK1),
							.iRST(DLY_RST_1)
						);
//----------------------------------------------------------------------------
//---------------------CAMERA1 RAW2RGB MODULE and SIGNALS---------------------							
wire [7:0] 	mD5M_R1; 		// intermediate signal
wire [7:0] 	mD5M_G1; 		// intermediate signal
wire [7:0] 	mD5M_B1; 		// intermediate signal
wire 		mD5M_DVAL1; 	// intermediate signal
//
RAW2RGB				U1B	(	.iCLK(D5M_PIXCLK1),
							.iRST(DLY_RST_1),
							.iDATA(cD5M_DATA1),
							.iDVAL(cD5M_DVAL1),
							.oRed(mD5M_R1),
							.oGreen(mD5M_G1),
							.oBlue(mD5M_B1),
							.oDVAL(mD5M_DVAL1),
							.oLine_No(Line_No1),
							.iX_Cont(X_Cont1),
							.iY_Cont(Y_Cont1)
);

//----------------------------------------------------------------------------
//--------------------------------------------------------------------------------		

wire 		ff_full1;
wire [10:0]	Line_No1;
reg	 [7:0]	GRAY1;

always @(posedge D5M_PIXCLK1 or negedge RST_N) begin
	if (!RST_N)
		GRAY1	<= 0;
	else 
		GRAY1	<= ((mD5M_R1>>2)+(mD5M_R1>>4))+((mD5M_G1>>1)+(mD5M_G1>>4))+(mD5M_B1>>3);
end

				 
//------------------------------CAMERA_FIFO2--------------------------------------	

assign 		w_BE_N6 = 4'b0000;
reg  [31:0]	w_data1;
reg			winc1;

reg 		gD5M_DVAL1; 	// intermediate signal	

always @(posedge D5M_PIXCLK0 ) begin
		gD5M_DVAL1	<= mD5M_DVAL1;
end	

reg	 [1:0]	byte_no1,pre_byte_no1;
always @(posedge D5M_PIXCLK1 or negedge RST_N)begin
	if (!RST_N)begin
		byte_no1 	<= 0;
	end
	else begin
		if (mD5M_DVAL1) begin
			byte_no1	<=	byte_no1 + 2'b01;
			case (byte_no1)
				2'b00: w_data1[7:0]		<=	GRAY1[7:0];
				2'b01: w_data1[15:8]	<=	GRAY1[7:0];
				2'b10: w_data1[23:16]	<=	GRAY1[7:0];
				2'b11: w_data1[31:24]	<=	GRAY1[7:0];
			endcase
		end
	end
end

always @ (posedge D5M_PIXCLK1) begin
	pre_byte_no1 <= byte_no1;
	if ((byte_no1 == 2'b00)&&(pre_byte_no1 == 2'b11))
		winc1 <= 1;
	else
		winc1 <= 0;
end	


always @ (posedge SRAM_CLK  or negedge Line_No1[0]) begin
  if (!Line_No1[0]) begin
    w_address6 	<= {Line_No1[10:1],7'b0000000}+{Line_No1[10:1],5'b00000}+19'h25800;	// 640 pixels
  end
  else begin
	if (w_port_avai6 && !w_stop6)
		w_address6 <= w_address6 + 1'b1;
  end
end

fifo1	U3B (
					.rdata(w_data6),
					.wfull(ff_full1),
					.rempty(w_stop6),
					.wdata(w_data1),
					.winc(winc1), .wclk(~D5M_PIXCLK1), .wrst_n(DLY_RST_1),
					.rinc(w_port_avai6), .rclk(SRAM_CLK), .rrst_n(DLY_RST_1)
				 );							
///////////////////////////////////////////////////////////////////////////////				 

				 

//////////////////////////////////////////////////////////////////				 			 						
SEG7_LUT_8 			U4	(	.oSEG0(oHEX0_D),.oSEG1(oHEX1_D),
							.oSEG2(oHEX2_D),.oSEG3(oHEX3_D),
							.oSEG4(oHEX4_D),.oSEG5(oHEX5_D),
							.oSEG6(oHEX6_D),.oSEG7(oHEX7_D),
							.iDIG({Frame_Cont0[15:0],Frame_Cont1[15:0]}) );
//DEBOUNCE	DEBOUNCE_ins (.iCLK(iCLK_50),.iSW(iKEY[0]),.oSW(RST_N));

Reset_Delay			U5	(	.iCLK(iCLK_50),
							.iRST(iKEY[0]),
							.oRST_0(DLY_RST_0),
							.oRST_1(DLY_RST_1),
							.oRST_2(DLY_RST_2),
							.oRST_3(DLY_RST_3),
							.oRST_4(DLY_RST_4)
						);
VgaPll		U6	(	.inclk0(iCLK_50),
					.c0(CLK_25),
					.c1(SRAM_CLK),
					.c2(DISP_CLK));

//clk_mng		U7	(.iCLK_50(iCLK_50), .iCLK_28(iCLK_28),.camera_CLK(camera_CLK),
//						 .SRAM_CLK(SRAM_CLK), .VGA_CLK(VGA_CLK), .CLK_D(CLK_D));

I2C_CCD_Config 		U8A	(	//	Host Side
							.iCLK(iCLK_50),
							.iRST_N(DLY_RST_2),
							.iZOOM_MODE_SW(iSW[16]),
							.iEXPOSURE_ADJ(iKEY[1]),
							.iEXPOSURE_DEC_p(iSW[0]),
							//	I2C Side
							.I2C_SCLK(GPIO_0[20]),
							.I2C_SDAT(GPIO_0[19]),
							.iSW(iSW));


I2C_CCD_Config 		U8B	(	//	Host Side
							.iCLK(iCLK_50),
							.iRST_N(DLY_RST_2),
							.iZOOM_MODE_SW(iSW[16]),
							.iEXPOSURE_ADJ(iKEY[1]),
							.iEXPOSURE_DEC_p(iSW[0]),
							//	I2C Side
							.I2C_SCLK(GPIO_1[20]),
							.I2C_SDAT(GPIO_1[19]),
							.iSW(iSW[4:1]));					
					
DISPARITY	U9 (
							.iSRAM_CLK(SRAM_CLK),
							.iCLK_D(DISP_CLK),
							.iRST_N(RST_N),
//--Read Port 2
							.r_address2(r_address2),
							.r_stop2(r_stop2),
							.r_data2(r_data2),
							.r_data_avai2(r_data_avai2),
//--Read Port 3
							.r_address3(r_address3),
							.r_stop3(r_stop3),
							.r_data3(r_data3),
							.r_data_avai3(r_data_avai3),
//--Write Port 7
							.w_address7(w_address7),
							.w_stop7(w_stop7),
							.w_data7(w_data7),
							.w_BE_N7(w_BE_N7),
							.w_port_avai7(w_port_avai7),
							.SW(iSW)
);


VgaController	U10 (//	Host Side	
						.r_address1(r_address1),
						.r_stop1(r_stop1),
						.r_data1(r_data1),
						.r_data_avai1(r_data_avai1),		
				//	VGA Side
						.oVGA_R(oVGA_R),
						.oVGA_G(oVGA_G),
						.oVGA_B(oVGA_B),
						.oVGA_H_SYNC(oVGA_HS),
						.oVGA_V_SYNC(oVGA_VS),
						.oVGA_SYNC(oVGA_SYNC_N),
						.oVGA_BLANK(oVGA_BLANK_N),
				// user
						.iVGA_CLK(CLK_25),
						.iSRAM_CLK(SRAM_CLK),
						.iRST_N(DLY_RST_4),
						.iSW(iSW),
						.oRequest(oRequest)
						);


wire oRequest;

Multi_Ports_SRAM_Ctrl	U11	(
							.iSRAM_CLK(SRAM_CLK),		// input clock
							.iRST_N(iKEY[0]),
							.iSW(iSW),

// --SRAM interface ------
							.oSRAM_CLK(oSRAM_CLK),
							.oSRAM_A(oSRAM_A),		// output address
							.SRAM_DQ(SRAM_DQ),		// DATA INPUT and OUTPUT port
							.oSRAM_ADSC_N(oSRAM_ADSC_N),	// controller address status
							.oSRAM_ADSP_N(oSRAM_ADSP_N),	// processor address status
							.oSRAM_ADV_N(oSRAM_ADV_N),	// advance input signal (burst address advance)
							.oSRAM_BE_N(oSRAM_BE_N), 	// Byte write enable
							.oSRAM_CE1_N(oSRAM_CE1_N), 	// chip enable 1
							.oSRAM_CE2(oSRAM_CE2),		// chip enable 2
							.oSRAM_CE3_N(oSRAM_CE3_N),	// chip enable 3
							.SRAM_DPA(SRAM_DPA),		// Parity data
							.oSRAM_GW_N(oSRAM_GW_N),		// global write
							.oSRAM_OE_N(oSRAM_OE_N),		// output enable
							.oSRAM_WE_N(oSRAM_WE_N),	// write enable
							
//--Read Port 1
							.r_address1(r_address1),
							.r_stop1(r_stop1),
							.r_data1(r_data1),
							.r_data_avai1(r_data_avai1),

//--Read Port 2
							.r_address2(r_address2),
							.r_stop2(1),//(r_stop2),
							.r_data2(r_data2),
							.r_data_avai2(r_data_avai2),
//--Read Port 3
							.r_address3(r_address3),
							.r_stop3(1),//(r_stop3),
							.r_data3(r_data3),
							.r_data_avai3(r_data_avai3),
//--Read Port 4
							.r_address4(r_address4),
							.r_stop4(1),//(r_stop4),
							.r_data4(r_data4),
							.r_data_avai4(r_data_avai4),
//--Write Port 5
							.w_address5(w_address5),
							.w_stop5(w_stop5),
							.w_data5(w_data5),
							.w_BE_N5(w_BE_N5),
							.w_port_avai5(w_port_avai5),
//--Write Port 6
							.w_address6(w_address6),
							.w_stop6(w_stop6),//(w_stop6),
							.w_data6(w_data6),
							.w_BE_N6(w_BE_N6),
							.w_port_avai6(w_port_avai6),
//--Write Port 7
							.w_address7(w_address7),
							.w_stop7(1),//(w_stop7),
							.w_data7(w_data7),
							.w_BE_N7(w_BE_N7),
							.w_port_avai7(w_port_avai7),
//--Write Port 8
							.w_address8(w_address8),
							.w_stop8(1),//(w_stop8),
							.w_data8(w_data8),
							.w_BE_N8(w_BE_N8),
							.w_port_avai8(w_port_avai8)
							);
	assign LEDR = {!rD5M_FVAL0,!rD5M_FVAL1,2'b00};
//--Read Port 1
	wire	[18:0]	r_address1;
	wire			r_stop1;
	wire	[31:0]	r_data1;
	wire			r_data_avai1;
//--Read Port 2
	wire	[18:0]	r_address2;
	wire			r_stop2;
	wire	[31:0]	r_data2;
	wire			r_data_avai2;
//--Read Port 3
	wire	[18:0]	r_address3;
	wire			r_stop3;
	wire	[31:0]	r_data3;
	wire			r_data_avai3;
//--Read Port 4
	wire	[18:0]	r_address4;
	wire			r_stop4;
	wire	[31:0]	r_data4;
	wire			r_data_avai4;
//--Write Port 5
	reg		[18:0]	w_address5;
	wire			w_stop5;
	wire	[31:0]	w_data5;
	wire	[3:0]	w_BE_N5;
	wire			w_port_avai5;
//--Write Port 6
	reg		[18:0]	w_address6;
	wire			w_stop6;
	wire	[31:0]	w_data6;
	wire	[3:0]	w_BE_N6;
	wire			w_port_avai6;
//--Write Port 7
	wire	[18:0]	w_address7;
	wire			w_stop7;
	wire	[31:0]	w_data7;
	wire	[3:0]	w_BE_N7;
	wire			w_port_avai7;
//--Write Port 8
	wire	[18:0]	w_address8;
	wire			w_stop8;
	wire	[31:0]	w_data8;
	wire	[3:0]	w_BE_N8;
	wire			w_port_avai8;

endmodule
